Several techniques in computer architecture and security require storing some state information, ranging from a few bits to half a dozen bytes, for memory regions, usually the size of cache lines. These state bits are commonly stored physically with the cache lines and occasionally in separate ad hoc structures like a speculative cache. Such schemes suffer two significant drawbacks. First, storing state bits in the cache incurs a sizeable hardware overhead, and makes the design inflexible. Second, the amount of memory that can be tracked by these schemes is bounded by the cache size. For example, in certain debugging models that store bits in cache lines to indicate if they contain allocated or initialized data, a cache line eviction forces the scheme to make conservative predictions of bugs and hence incurs false positives or false negative. Similarly, for hardware transactional memory, if a speculative cache line has to be evicted, the transaction must be aborted.
In modern processors, translation lookaside buffers (TLBs) store address translations from a virtual address (VA) to a physical address (PA). These address translations are generated by the operating system (OS) and stored in memory within page table data structures, which are used to populate the TLB. Generally, such translations are the only information stored in a TLB.